IS61NLF51218B

容量 9M
規格 512Kx18
電壓 3.3V
VccQ 2.5/3.3V
狀態 Prod
tKQ(ns) 6.5, 7.5
腳位數 BGA(119), QFP(100), BGA(165)
速度Mhz 133, 117
評論上一版本 F, IS61NLF51218A

IS61NLF51218B 特徵

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single Read/Write control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin QFP, 119-ball BGA, and 165- ball BGA packages
  • Power supply: NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVF: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
  • JTAG Boundary Scan for BGA packages
  • Industrial temperature available

概觀

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single Read/Write control pin , Clock controlled, registered address,

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS61NLF51218B-6 IS61NLF51218B-7
IS61NLF51218B-6-TR IS61NLF51218B-7-TR