The 18Meg product family features high-speed, low-
power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state,
device for networking and communications
applications. They are organized as 512K words by
36 bits and 1024K words by 18 bits, fabricated with
ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles
are eliminated when the bus switches from read to
write, or write to read. This device integrates a 2-bit
burst counter, high-speed SRAM core, and high-
drive capability outputs into a single monolithic
All synchronous inputs pass through registers are
controlled by a positive-edge-triggered single clock
input. Operations may be suspended and all
synchronous inputs ignored when Clock Enable,
/CKE is HIGH. In this state the internal device will
hold their previous values.
All Read, Write and Deselect cycles are initiated by
the ADV input. When the ADV is HIGH the internal
burst counter is incremented. New external
addresses can be loaded when ADV is LOW.
Write cycles are internally self-timed and are
initiated by the rising edge of the clock inputs and
when /WE is LOW. Separate byte enables allow
individual bytes to be written.
A burst mode pin (MODE) defines the order of the
burst sequence. When tied HIGH, the interleaved
burst sequence is selected. When tied LOW, the
linear burst sequence is selected.