IS61NLP204836B-166TQLI-TR

容量 72M
規格 2Mx36
電壓 3.3V
VccQ 2.5/3.3V
狀態 Prod
tKQ(ns) 2.6, 3.1, 3.5
腳位數 QFP(100), BGA(165, 119)
速度Mhz 250, 200, 166
評論上一版本 P

IS61NLP204836B-166TQLI-TR 特徵

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
  • Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
  • JTAG Boundary Scan for PBGA packages
  • Industrial temperature available

概觀

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single R/W (Read/Write) control pin , Clock controlled, registered address,

 

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