IS61NVF25672-7

容量 18M
規格 256Kx72
電壓 2.5V
VccQ 2.5V
狀態 Prod
tKQ(ns) 6.5, 7.5
腳位數 BGA(209)
速度Mhz 133, 117
評論上一版本 F

IS61NVF25672-7 特徵

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single Read/Write control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 165-ball PBGA and 209- ball (x72) PBGA packages
  • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
  • JTAG Boundary Scan for PBGA packages
  • Industrial temperature available

概觀

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single Read/Write control pin , Clock controlled, registered address,

 

相關IC编號

IS61NVF25672-7-TR IS61NVF25672-6 IS61NVF25672-6-TR