IS61NVP51236B-200TQI

容量 18M
規格 512Kx36
電壓 2.5V
VccQ 2.5V
狀態 Prod
tKQ(ns) 2.6, 3.0
腳位數 QFP(100), BGA(119, 165)
速度Mhz 250, 200
評論上一版本 P, IS61NVP51236

IS61NVP51236B-200TQI 特徵

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, data and Internal self-timed write cycle Individual Byte Write Control
  • control Interleaved or linear burst sequence control using MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs /CKE pin to enable clock and suspend
  • operation JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages
  • Power supply: NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NVVP: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%) JTAG Boundary Scan for BGA packages
  • Commercial, Industrial and Automotive (x36) temperature support
  • Lead-free available

概觀

The 18Meg product family features high-speed, low- power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 512K words by 36 bits and 1024K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high- drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, /CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when /WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.

 

相關IC编號

IS61NVP51236B-200TQI-TR IS61NVP51236B-200B3I-TR IS61NVP51236B-200B3LI-TR IS61NVP51236B-200TQL-TR
IS61NVP51236B-200B3 IS61NVP51236B-200B3L IS61NVP51236B-200TQ IS61NVP51236B-200TQLI
IS61NVP51236B-200B3-TR IS61NVP51236B-200B3L-TR IS61NVP51236B-200TQ-TR IS61NVP51236B-200TQLI-TR
IS61NVP51236B-200B3I IS61NVP51236B-200B3LI IS61NVP51236B-200TQL