容量 4M
規格 128Kx36
電壓 2.5V
VccQ 2.5V
狀態 Prod
tKQ(ns) 2.6, 3.1
腳位數 BGA(119), QFP(100), BGA(165)
速度Mhz 250, 200
評論上一版本 P/SCD, ECC feature, IS61VPS12836A

IS61VPS12836EC-200TQLI 特徵

  • Internal self-timed write cycle Individual Byte Write Control and Global Write
  • Clock controlled, registered address, data and control
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth expansion and address pipelining
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Single cycle deselect
  • Snooze MODE for reduced-power standby
  • JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages
  • Power supply: LPS: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) VPS: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) JTAG Boundary Scan for BGA packages Industrial and Automotive temperature support
  • Lead-free available


The 4Mb product family features high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LPS/VPS12836EC are organized as 131,072 words by 36bits. The IS61(64)LPS/VPS12832EC are organized as 131,072 words by 32bits. The IS61(64)LPS/VPS25618EC are organized as 262,144 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive- edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (/BWE) input combined with one or more individual byte write signals (/BWx). In addition, Global Write (/GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either /ADSP (Address Status Processor) or /ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the /ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order. Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.



IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS61VPS12836EC-200TQLI-TR IS61VPS12836EC-250B2-TR
IS61VPS12836EC-200B2 IS61VPS12836EC-250B2I
IS61VPS12836EC-200B2-TR IS61VPS12836EC-250B2I-TR
IS61VPS12836EC-200B2I IS61VPS12836EC-250B2L
IS61VPS12836EC-200B2I-TR IS61VPS12836EC-250B2L-TR
IS61VPS12836EC-200B2L IS61VPS12836EC-250B2LI
IS61VPS12836EC-200B2L-TR IS61VPS12836EC-250B2LI-TR
IS61VPS12836EC-200B2LI IS61VPS12836EC-250B3
IS61VPS12836EC-200B2LI-TR IS61VPS12836EC-250B3-TR
IS61VPS12836EC-200B3 IS61VPS12836EC-250B3I
IS61VPS12836EC-200B3-TR IS61VPS12836EC-250B3I-TR
IS61VPS12836EC-200B3I IS61VPS12836EC-250B3L
IS61VPS12836EC-200B3I-TR IS61VPS12836EC-250B3L-TR
IS61VPS12836EC-200B3L IS61VPS12836EC-250B3LI
IS61VPS12836EC-200B3L-TR IS61VPS12836EC-250B3LI-TR
IS61VPS12836EC-200B3LI IS61VPS12836EC-250TQL
IS61VPS12836EC-200B3LI-TR IS61VPS12836EC-250TQL-TR
IS61VPS12836EC-200TQL IS61VPS12836EC-250TQLI
IS61VPS12836EC-200TQL-TR IS61VPS12836EC-250TQLI-TR