規格 | 64Mx16 |
---|---|
類型 | DDR3 |
電壓 | 1.5V |
刷新 | 8K |
速度 | 125 = up to 800Mhz (DDR3 - 1600) |
腳位/封裝 | BGA(96) |
狀態 | Prod |
型號別 | IBIS |
評注 | ECC |
產品系列 | 46 = 車規DDR/DDR2/DDR3/DDR4 |
總線寬度 | 16 = x16 |
字數 | 640 = 64M |
代/版本 | E |
CL(CAS延遲) | K = 11 |
焊接 | L = SnAgCu |
温規 | A2 = 車規 (-40C to +105°C) |
外包裝 | 卷轴包 |
IS46TR16640ED-125KBLA2-TR 特徵
- Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
- High speed data transfer rates with system frequency up to 800 MHz
- 8 internal banks for concurrent operation
- 8n-bit pre-fetch architecture
- Programmable CAS Latency
- Programmable Additive Latency: 0, CL-1,CL-2
- Programmable CAS WRITE latency (CWL) based on tCK
- Programmable Burst Length: 4 and 8
- Programmable Burst Sequence: Sequential or Interleave
- BL switch on the fly
- Auto Self Refresh(ASR)
- Self Refresh Temperature(SRT) ECC
- Single bit error correction (per 64-bits)
- Restrictions on Burst Length and Data Mask OPTIONS
- Configuration: 128Mx8 64Mx16
- Package: 96-ball FBGA (9mm x 13mm) for x16 78-ball FBGA (8mm x 10.5mm) for x8 SPEED BIN Speed Option 15H 125K MAY 2017
- Refresh Interval: 7.8 μs (8192 cycles/64 ms) Tc= -40°C to 85°C 3.9 μs (8192 cycles/32 ms) Tc= 85°C to 105°C 1.95 μs (8192 cycles/16ms)Tc=105°C to 125°C
- Partial Array Self Refresh
- Asynchronous RESET pin
- TDQS (Termination Data Strobe) supported (x8 only)
- OCD (Off-Chip Driver Impedance Adjustment)
- Dynamic ODT (On-Die Termination)
- Driver strength : RZQ/7, RZQ/6 (RZQ = 240 )
- Write Leveling